1. Technical Field
The present invention is directed to a process for semiconductor, and, specifically to a technique for introducing boron dopant into a semiconductor substrate.
2. Art Background
In integrated circuit fabrication, dopants are frequently introduced into semiconductor substrates to provide the semiconductor substrate with certain electrical characteristics. High energy implants (i.e. implants using an implant energy in excess of about 0.5 MeV) are an increasingly important method for introducing dopants into semiconductor substrates because the dopants and/or defects are implanted to the desired depth (i.e. about 0.5 .mu.m to about 5 .mu.m) beneath the surface of the substrate. High energy implants are used for forming retrograde wells for complementary metal-oxide semiconductor (CMOS), latch up immunity improvement, buried layers for soft-error reduction in dynamic random access memories, bipolar subcollectors, and proximity gettering centers. At these high energies, the dopant profile is tailored to provide the desired concentration of dopant within the desired distance from the surface of the semiconductor substrate. As noted in Kuroi, T., et al., "Bipolar Transistor with a Buried Layer Formed by High-Energy Ion Implantation for Subhalf-Micron Bipolar Complementary Metal Oxide Semiconductor LSIs," Jpn. J. Appl. Phys., Vol. 33 Pt. 1, No. 1B (1994) high energy implants are useful because the buried layer (i.e. the region of the substrate below the surface with a dopant concentration above a certain threshold amount) is formed without growing an epitaxial layer on the semiconductor substrate to place the buried layer at the desired depth below the substrate surface. In Kuroi et al., the buried layer is formed using a phosphorous ion implant at 1.5 MeV with doses ranging from 1.times.10 .sup.13 /cm.sup.2 to 1.times.10.sup.15 /cm.sup.2, followed by an anneal. The anneal conditions described in Kuroi et al. are either a furnace anneal at 1000.degree. C. for 1 hour, or a rapid thermal anneal at 1000.degree. C. for 30 seconds in a nitrogen atmosphere. However, Kuroi et al. note that the damage caused by such high energy implants, and the high leakage currents that result therefrom must be reduced.
Cheng, J. Y., et. al., "Formation of extended defects in silicon by high energy implantation of B and P" J. Appl. Phys. Vol. 80, No. 4, pp. 2105-2112 (August 1996) observe the effects of high energy boron (1.5 MeV) and phosphorus (2.6 MeV) implants in silicon. Cheng et al. observe the formation of long dislocation dipoles (referred to as threading dislocations) after a furnace anneal of the implanted substrates. These dislocations were generated in the substrate at the approximate depth of the mean projected range of the implanted ions. The dislocations were observed to grow up to the substrate surface and were found to cause high junction leakage current. Cheng et al. investigated the dislocation density as a function of the dopant (boron or phosphorous), implant dose, depth, and the substrate (Czochralski (Cz) substrates, float zone (FZ) grown (100) Si substrates, and epitaxial silicon layers grown on (100) silicon (epi) substrates).
According to Cheng et al., the threading dislocation density caused by high energy boron implant is much higher in Czochralski substrates than in the other types of substrates after a post implant anneal at 900.degree. C. for 30 minutes. Cheng et al. showed that the dislocation density has strong dose dependence, with a maximum defect density observed at doses of about 1.times.10.sup.14 /cm.sup.2. The density of threading dislocations was found to increase with increasing distance from the surface. Cheng et al. proposed a two step anneal wherein the substrate is first annealed at 700.degree. C. for about 20 hours followed by an anneal at 900.degree. C. to reduce the formation of threading dislocation during the 900.degree. C. anneal. Cheng et al. observed that the two-step anneal reduced the density of threading dislocations in boron-implanted Czochralski substrates and boron-implanted epitaxial silicon substrates.
However, the 20 hour anneal suggested by Cheng et al. is simply too long to be practical in commercial processes for semiconductor processing. Consequently, processes that reduce the threading dislocations caused by high energy implants and that are compatible with commercial processes for device fabrication are sought.